Lab Spotlights — Computer Engineering


High Level Systems Design Lab
Forrest Brewer


The High Level Systems Design lab builds circuits. Our lab encompasses the stages of electronic design from the development of tools for exploring what to build to the layout of transistors for the fabrication of prototype chips. Once an integrated circuit is fabricated we test the final design to verify its construction and incorporate the results into our body of knowledge used to built the future chips. 

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Radiation Hardened Electronics
Space exploration, physics experiments, power plants and medical technology all share a need for electronics which survive in extreme environments, where electromagnetic radiation can destroy traditional digital electronics. Our lab develops tools that enable the design of circuits able to withstand the impact of radiation and still function successfully. This means when a circuit needs to survive inside of a particle accelerator we are able to build a design for that or if a robot needs to be controlled in space, we can build circuits for that, too.

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Asynchronous Architectures & CAD Tools
Our lab explores designs where the clock is missing and the computation is carried out using event driven operations. We build CAD tools to verify and synthesize closed models of high performance asynchronous systems. 

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Mixed Signal Circuit/System Design
Mixed signal design intermingles the traditional paradigm of boolean logic with the physics of analog electronics to built novel integrated circuits. Our research considers how concepts like integrated charge enable successful designs of serial links in a design space where traditional metrics would predict failure. 

Bitstream Control & Signal Processing

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This research involves developing formal methodologies and techniques for designing digital circuits around computation on raw bitstreams.  The results are digital circuits which deliver low latency, low complexity, and low power performance for applications like active noise cancellation and micro-electro-mechanical systems (MEMS) control.

Professor Brewer's:

Learning-Based Multimedia (LBMM) Lab
Kwang-Ting (Tim) Cheng

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The Learning-Based Multimedia Lab focuses on research projects for a wide range of multimedia applications. Our current research directions include:

  • Mobile Computer Vision: There is an explosive demand of running computer vision (CV) algorithms on low power mobile devices, such as smartphones. However, most existing CV algorithms are either too computational expensive for mobile devices or lack sufficient robustness. Thus they cannot provide a satisfactory user experience. We focus on: 1) designing new light-weight and robust algorithms, and 2) adapting existing algorithms to mobile CPU and/or GPU, for fundamental computer vision components, such as feature extraction, recognition and tracking, etc.
  • Heterogeneous Mobile Computing: Mainstream mobile application processors (AP) are accelerator-rich, heterogeneous multi-core SoCs. It provides high computing capability with ultra-low power consumption, yet mapping algorithms to such platforms is a challenge task due to a huge and complex design space. We are developing a method to guide the app developers to explore smart utilization of platform's computing resource and to adapt algorithms for energy minimization.
  • Mobile Medical Image Viewing: High-quality, augmented bio-sensor and the increasing computing power enables medical imaging systems, which only available in clinic workstations in the past, a viable application on mobile devices. We investigate approaches to deliver an optimized user experience per energy unit, from both computing and displaying aspects, for such emerging applications.

Professor Cheng's:

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Novel Electronic Devices and Computing Systems Laboratory
Dmitri Strukov

Research Focus:

  • Novel electronic devices with a particular focus on resistive switching effects
  • Circuit design for novel electronic devices
  • Emerging architectures for computing and design automation

Particular Focus - CMOL Technology:

The basic idea of CMOL circuits (standing for Cmos + MOLecular-scale devices) is to combine the advantages of the CMOS technology including its flexibility and high fabrication yield with those of ultra dense stackable crosspoint devices, e.g. those based on resistive switching phenomena. The nanoscale devices are naturally incorporated into the crossbar fabric enabling very high functional density at acceptable fabrication cost. In particular, CMOL circuits are especially suitable for digital memories, reconfigurable computing and bio-inspired signal processing.

Professor Strukov's:

Nanoelectronics Research Lab
Kaustav Banerjee

The Banerjee group focuses on various aspects of nanoelectronics research, including fundamental physics, electrical and thermal modeling, robust circuit/architecture design, as well as nanomaterial synthesis and nanostructure/device fabrication. Work in the Nanoelectronics Research Lab (NRL) falls into one of the following areas:

  • Carbon Nanoelectronics: Physics, technology, and applications of graphene and carbon nanotubes in electronics, energy harvesting /storage and bio/medicine
  • Green Electronics: Sub-kT/q devices such as tunneling-FETs and NEMS; ultra low-voltage circuit and system design
  • Nano-Devices & 3-D ICs: Emerging CMOS technologies such as FinFET and Nanowire-FET; innovative digital and memory devices; 3-D heterogeneous ICs; device-circuit interactions
  • Nanoscale Interconnects: Ultra high-frequency modeling/extraction for VLSI interconnects and passive elements; exploration of emerging interconnect/passive structures and technologies

Professor Banerjee's:


Scalable Energy-efficient Architecture Lab (SEALab)
Yuan Xie

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SEALab aims at leveraging emerging technologies (with emphasize on 3D integration and emerging nonvolatile memory) for edge-cutting applications (e.g., machine learning and bioinformatics).

SEALab distinguishes itself by strong cross-layer researches going from device to application, and works on circuit design, EDA tools, and computer architecture at the same time. Recent research highlights are as follows:

sealab 3d design

3D Design & Design Automation
The architecture we proposed in 2012 turns to the world-first 3D GPU on the market (AMD Fury X). Our recent researches including cost analysis for 2.5D/3D integration, heterogonous integration, and 3D based hardware security study.

sealab youtube video

Modeling, Architecture and Application for Emerging Nonvolatile Memory
We help the community to understand NVM’s pros and cons for better utilizing them to improve the future computing systems, e.g., IoT, GPGPU, NoC, and Data Center. We are also interested in utilizing NVM’s nonvolatility feature for normally-off computing, check-pointing, and persistent memory.

Energy-efficient Hardware for Machine Learning and Neuromorphic Computing
We explore optimizing machine learning applications on parallel and heterogonous architecture as well as reconfigurable fabric. We also leverage emerging technologies for machine learning and bio-inspired applications, e.g., 3D stacked high bandwidth memory, low-power NVM.

Professor Xie's:

Test and Verification Lab
Li-C. Wang

test and verfication lab research graph

The Test and Verification Lab leverages machine learning algorithms to assist in the process of knowledge discovery during the design and manufacturing process.

The application of our research lies in  two fronts:

Test:  During the test process, numerous measurements are performed on each chip to ensure that each chip meets its design specifications and is working properly.  We examine ways to leverage this data to reveal new insights into the manufacturing process that can then be used to create positive outcomes for the company.  So examples of these outcomes from previous projects include but are not limited to:

  • Improving Quality: Using statistical methodologies to complement existing testing for the purpose of screening future in-field failures for high-reliability products;
  • Improving Yield: Identifying the key process parameters that are contributing to abnormal yield fluctuations.
  • Reducing Cost: Identifying redundant tests by constructing predictive models based on remaining tests.

Verification: Functional verification is an iterative process since the design changes over time. Tons of machine hours are spent on simulating the tests in hope of covering all corners of the design and capturing functional bugs. Valuable knowledge is embedded in the simulation data and regression tests accumulated along the verification process. Data mining techniques can be applied to extract the knowledge and leverage them to improve the verification efficiency. Here are two example applications from previous projects:

  • Reducing simulation cost: Building statistical models to filter out ineffective tests for cutting down the cost of simulation time and licenses.
  • Improving testbench: Extracting rules from novel tests to present to the verification engineers so that they can improve the test generation.

Professor Wang's:

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VLSI CAD Lab
Margaret Marek-Sadowska

Since its inception in 1990, many researchers including graduate students, scholars, faculty, and industry associates have actively participated in the lab's activities. Members of the VLSI CAD Lab exhibit diverse research interests in the field of Electronic Design Automation ranging from logic synthesis to manufacturing and more.

Recent research activities include:

  • Electromigration (EM): has become a serious problem for integrated circuits due to feature size shrinking. Our target is to detect hotspot wires/vias that are prone to EM failure, and provide EM design guidelines and intelligent method to fix hotspot wires/vias.
  • Heterogeneous 3D Chip: recently, CPU and GPU have been integrated in one chip. No exploration tool exists for studying a CPU+GPU, cache, and NoC together on 3D architectures. We are developing a tool for 3D heterogeneous structures that allows designers to quantify various architectural solutions from a physical design standpoint.
  • VeSFET Physical Design: Vertical Slit Field Effect Transistor (VeSFET) is a novel twin-gate 3D device. VeSFET-based designs have many advantages such as low power, regular layout, small footprint area and easy 3D integration. Our research includes VeSFET physical design (placement & routing), testing strategies and low power applications.
  • Testing Analog Components in SoCs: Analog components in SoC designs are difficult to test within the digital design verification flow. Components are simulated and verified using SPICE, which is time consuming for complex components. We are working on a machine learning method that automatically creates behavioral System Verilog macromodels that remove the need for SPICE simulation and can be tested using EDA digital design tools.

Professor Marek-Sadowska's: