Page last updated on 2016 August 17

This **Appendix B to B. Parhami's CV** contains a partial list of citations of Professor Parhami's work by other scholars. Numbers in brackets refer to items in his list of publications. These are research papers and other documents that Professor Parhami has encountered in his own literature review. Many more citations exist. For example, as of April 30, 2013, Google Scholar lists 1102 citations of Professor Parhami's book on computer arithmetic [179], 269 citations of his book on parallel processing [162], 162 citations of his 1994 *IEEE Trans. Reliability* paper on voting algorithms [101], and 157 citations of his 1990 *IEEE Trans. Computers* paper on generalized signed-digit number systems [66].

**[Abde11]** Abdel-Hafeez, S. and A. Gordon-Ross, "A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic,"
*IEEE Trans. VLSI Systems*, Vol. 19, No. 6, pp. 1023-1033, June 2011.

Cites the computer arithmetic book [179].

**[AbuG99]** Abu-Ghazaleh, N. and P. A. Wilsey, "Managing Control Synchrony on SIMD Machines—A Survey,"
*Advances in Computers*, ed. by M. Zelkovitz, 1999, pp. 240-303.

Cites the 1995 paper on SIMD machines [105].

**[Aiel01]** Aiello, W., S. N. Bhatt, F. R. K. Chung, A. L. Rosenberg, and R. K. Sitaraman, "Augmented Ring Networks,"
*IEEE Trans. Parallel and Distributed Systems*, Vol. 12, No. 6, pp. 598-609, June 2001.

Cites the 1996 SPDP paper on PRC rings [131].

**[Akop97]** Akopian, D. A., O. Vainio, S. S. Agaian, and J. T. Astola, "SBNR Processor for Stack Filters,"
*IEEE Trans. Circuits and Systems II*, Vol. 44, No. 3, pp. 197-208, March 1997.

Cites the 1988, 1990, and 1993 papers on GSD arithmetic [56], [66], [86].

**[Ali96]** Ali, A. and R. Vaidyanathan, "Exact Bounds on Running ASCEND/DESCEND and FAN-IN Algorithms on Synchronous Multiple-Bus Networks,"
*IEEE Trans. Parallel and Distributed Systems*, Vol. 7, No. 8, pp. 783-790, August 1996.

Cites the 1993 *IEEE TPDS* paper on meshes with row/column buses [90].

**[Alio11]** Alioto, M., G. Palumbo, and M. Poli, "Optimized Design of Parallel Carry-Select Adders,"
*Integration, the VLSI J.*, Vol. 44, No. 1, pp. 62-74, January 2011.

Cites the the computer arithmetic book [179].

**[Amin06]** Amin, A., "High-Speed Self-Timed Carry-Skip Adder,"
*IEE Proc. Circuits, Devices, and Systems*, Vol. 153, No. 6, pp. 574-582, December 2006.

Cites the computer arithmetic book [179].

**[Amin07]** Amin, A. A., "Area-Efficient High-Speed Carry Chain,"
*Electronics Letters*, Vol. 43, No. 23, November 8, 2007.

Cites the computer arithmetic book [179].

**[Amin10]** Amin, A. and M. W. Shinwari, "High-Radix Multiplier-Dividers: Theory, Design, and Hardware,"
*IEEE Trans. Computers*, Vol. 59, No. 8, pp. 1009-1022, August 2010.

Cites the 1990 *IEEE TC* paper on GSD numbers [66].

**[Ande75]** Anderson, J. A. and G. J. Lipovski, "A Virtual Memory for Microprocessors,"
*Proc. 2nd Symp. Computer Architecture*, pp. 80-84, January 1975.

Cites the 1972 RAPID paper [2].

**[Ante05]** Antelo, E., T. Lang, P. Montuschi, and A. Nannarelli, "Digit-Recurrence Dividers with Reduced Logical Depth,"
*IEEE Trans. Computers*, Vol. 54, No. 7, pp. 837-851, July 2005.

Cites the 2003 *IEEE TC* paper on high-radix division [207].

**[Arms93]** Armstrong, J. R. and F. G. Gray, *Structured Logic Design with VHDL*,

Prentice Hall, 482 pp., 1993, ISBN = 0-13-855206-1.

Contains an extensive description of URISC on pp. 240-251. Mentions that the design is due to Mavaddat and Parham (sic), but does not list the 1988 URISC paper [54] among references.

**[Arms00]** Armstrong, J.R. and F.G. Gray, *VHDL Design Representation and Synthesis*,

Prentice Hall, 2nd ed., 2000, 651 pp., ISBN = 0-13-021670.

Contains an extensive description of URISC on pp. 245-257. Mentions that the design is due to Mavaddat and Parham (sic), but does not list the 1988 URISC paper [54] among references.

**[Arno93]** Arno, S., and F. S. Wheeler, "Signed Digit Representations of Minimal Hamming Weight,"
*IEEE Trans. Computers*, Vol. 42, No. 8, pp. 1007-1010, August 1993.

Cites the 1990 *IEEE TC* paper on generalized signed-digit representations [66].

**[Baja04]** Bajard, J.-C., and T. Plantard, "RNS Bases and Conversions,"
*Advanced Signal Processing Algorithms, Architectures, and Implemenatations XIV* (Proc. SPIE Conf. 5559), August 2004, pp. 60-69.

Cites the 1993 Asilomar Conf. paper on optimal RNS conversions [91] and the 1994 CAM on approximate sign detection [92].

**[Bati03]** Batina, L., S. B. Ors, B. Preneel, and J. Vandewalle, "Hardware Architectures for Public Key Cryptography,"
*Integration, the VLSI J.*, Vol. 34, Nos. 1-2, pp. 1-64, May 2003.

Cites the 1990 *IEEE TC* paper on generalized signed-digit representations [66].

**[Bein04]** Bein, D., W. W. Bein, and S. Latifi, "Optimal Embedding of Honeycomb Networks into Hypercubes,"
*Parallel Processing Letters*, Vol. 14, Nos. 3-4, pp. 367-375, 2004.

Cites the 2001 *IEEE TPDS* paper on honeycomb and diamond networks [191].

**[Beiu04]** Beiu, V., and M. Sulieman, "Optimal Practical Perceptron Addition Application to Single Electron Technology,"
*Proc. Int'l Conf. VLSI*, Las Vegas, NV, June 21-24, 2004, pp. 541-547.

Cites the 1999 and 2000 Asilomar Conf. papers on threshold circuits [174], [190].

**[Bell13]** Belloeil-Dupuis, S., R. Chotin-Avot, and H. Mehrez, "Exploring Redundant Arithmetics in Computer-Aided Design of Arithmetic Datapaths,"
*Integration, the VLSI J.*, Vol. 46, No. 2, pp. 104-118, March 2013.

Cites the book on computer arithmetic [259].

**[Berr74]** Berra, P. B., "Some Thoughts on the Future of Associative Memories/Processors in the Solution of Data Base Management Problems,"
*Proc. ACM SIGFIDET (now SIGMOD) Workshop on Data Description, Access, and Control*, May 1974, pp. 463-476.

Cites the 1972 RAPID paper [2].

**[Beuc02]** Beuchat, J.-L., and A. Tisserand, "Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices,"
*Proc. 12th Int'l Conf. Field-Programmable Logic and Applications*, 2002, LNCS #2438, pp. 513-522.

Cites the computer arithmetic book [179].

**[Bhar10]** Bharghava, R., R. Abinesh, S. Purini, and G. Regeti, "Inexact Decision Circuits: An Application to Hamming Weight Threshold Voting,"
*Proc. 23rd Int'l Conf. VLSI Design*, 2010, pp. 158-163.

Cites the 1994 *IEEE TR* paper on voting algorithms [101].

**[Blun02]** Blunden, B., *Virtual Machine Design and Implementation in C/C++*,

Worldware Publishing, 2002.

Cites the computer arithmetic book [179] on p. 148.

**[Bora83]** Boral, H. and D. J. DeWitt, "Database Machines: An Idea Whose Time Has Passed? — A Critique of the Future of Database Machines,"

in *Database Machines*, ed. By H.-O. Leilich and M. Missikoff, Springer-Verlag, 1983, pp. 166-?.

Cites the 1972 RAPID paper [2].

**[Bose84]** Bose, B., "Two Dimensional ARC Codes,"
*Proc. Fault-Tolerant Computing Symp.*, pp. 324-329, 1984.

Cites the *IEEE TC* 1978 code paper [28].

**[Bose84a]** Bose, B., "Unidirectional Error Correction/Detection for VLSI Memory,"
*Proc. 11th Int'l Symp. Computer Architecture*, pp. 242-244, January 1984.

Cites the *IEEE TC* 1978 arithmetic error codes paper [28].

**[Bose87]** Bose, B., "2-Dimensional Arithmetic Residue Check Codes,"
*Computers & Mathematics with Applications*, Vol. 13, Nos. 5/6, pp. 547-554, 1987.

Cites the *IEEE TC* 1978 arith. code paper [28].

**[Bris07]** Brisk, P., A. K. Verma, P. Ienne, and H. Parandeh-Afshar, "Enhancing FPGA Performance for Arithmetic Circuits,"
*Proc. 44th Design Automation Conf.*, June 2007, pp. 334-337.

Cites the computer arithmetic book [179].

**[Bron97]** Bronnimann, H., I. Z. Emiris, V. Y. Pan, and S. Pion, "Computing Exact Geometric Predicates Using Modular Arithmetic with Single Precision,"
*Proc. 13th Symp. Computational Geometry*, pp. 174-182, August 1997.

Cites the *Computers & Math.* 1994 paper on RNS sign detection [92].

**[Brug93]** Bruguera, J. D., E. Antelo, and E. L. Zapata, "Design of a Pipelined Radix-4 CORDIC Processor,"
*Parallel Computing*, Vol. 19, pp. 729-744, 1993.

Cites the *IEEE TC* 1988 recoded BSD paper [56].

**[Bush76]** Bush, J. A., G. J. Lipovski, S. Y. W. Su, J. K. Watson, and S. J. Ackerman, "Some Implementations of Segment Sequential Functions,"
*Proc. 3rd Symp. Computer Architecture*, pp. 178-185, January 1976.

Cites the 1972 RAPID paper [2].

**[CADE12]** Cadenas, J., G. M. Megson, R. S. Sherratt, and P. Huerta, "Fast Median Calculation Method," *Electronics Letters*, Vol. 48, No. 10, pp. 558-560, 2012.

Cites the book on computer arithmetic [176].

**[Cail74]** Caillouet, L. P. and B. D. Shriver, "An Integrated Approach to the Design of Fault Tolerant Computing Systems,"
*Conf. Record 7th Workshop Microprogramming*, pp. 12-24, September 1974.

Cites "Diagnostic and Microdiagnostic Techniques for Digital Systems," unpublished lecture notes for a short course, UCLA, March 1974.

**[Camp06]** Campobello, G. and M. Russo, "A Scalable VLSI Speed/Area Tunable Sorting Network,"
*J. Systems Architecture*, Vol. 52, No. 10, pp. 589-602, October 2006.

Cites the 1995 Asilomar Conf. paper on accumulative parallel counters [107].

**[Card83]** Cardenas, A. F., F. Alavian, and A. Avizienis, "Performance of Recovery Architectures in Parallel Associative Database Processors,"
*ACM Trans. Database Systems*, Vol. 8, No. 3, pp. 291-323, September 1983.

Cites the 1972 RAPID paper [2].

**[Card00]** Cardarilli, G. C., M. Re, R. Lojacono, and G. Ferri, "A Systolic Architecture for High-Performance Scaled Residue to Binary Conversion,"
*IEEE Trans. Circuits and Systems I*, Vol. 47, No. 10, pp. 1523-1526, October 2000.

Cites the 1995 *IEEE TC* paper on approximate CRT decoding [108].

**[Card15]** Cardenas, J. O., G. M. Megson, and R. S. Sherratt, "Median Filter Architecture by Accumulative Parallel Counters,"
*IEEE Trans. Circuits and Systems II*, Vol. 62, No. 7, pp. 661-665, July 2015.

Cites the 1995 Asilomar Conf. paper on accumulative parallel counters [107] and the 2000 book on computer arithmetic [179].

**[Carl01]** Carle, J., J.-F. Myoupo, and I. Stojmenovic, "Higher Dimensional Honeycomb Networks,"
*J. Interconnection Networks*, Vol. 2, No. 4, pp. 391-420, December 2001.

Cites the parallel processing book [162].

**[Chan02]** Chang, Y.-T. and K. T. Cheng, "Self-Referential Verification of Gate-Level Implementations of Arithmetic Circuits,"
*Proc. 39th Design Automation Conf.*, pp. 311-316, June 2002.

Cites the computer arithmetic book [179].

**[Cheu05]** Cheung, R. C. C., D.-U Lee, O. Mencer, W. Luk, and P. Y. K. Cheung, "Automating Custom-Precision Function Evaluation for Embedded Processors,"
*Proc. Int'l Conf. Compilers, Architectures and Synthesis for Embedded Systems*, San Francisco, September 24-27, 2005, pp. 22-31.

Cites the computer arithmetic book [179].

**[Cho03]** Cho, H.-J. and L.-Y. Hsu, "Generalized Honeycomb Torus,"
*Information Processing Letters*, Vol. 86, No. 4, pp. 185-190, 2003.

Cites the 2001 *IEEE TPDS* paper on honeycomb and diamond networks [191].

**[Choi02]** Choi, Y. and E. E. Swartzlander, Jr., "Design of a Hybrid Prefix Adder for Non-Uniform Input Arrival Times,"
*Advanced Signal Processing Algorithms, Architectures, and Implementations XII* (Proc. SPIE Int'l Symp.), July 2002.

Cites the computer arithmetic book [179].

**[Cope73]** Copeland, G. P., G. J. Lipovski, and S. Y. W. Su, "The Architecture of CASSM,"
*Proc. 1st Symp. Computer Architecture*, pp. 121-128, December 1973.

Cites the 1972 RAPID paper [2].

**[Coto05]** Cotofana, S., C. Lageweg, and S. Vassiliadis, "Addition Related Arithmetic Operations via Controlled Transport of Charge,"
*IEEE Trans. Computers*, Vol. 54, No. 3, pp. 243-256, March 2005.

Cites the computer arithmetic book [179].

**[Croo07]** Crookes, D., and M. Jiang, "Using Signed Digit Arithmetic for Low-Power Multiplication,"
*Electronics Letters*, Vol. 43, No. 11, pp. 613-614, 24 May 2007.

Cites the computer arithmetic book [179].

**[Dany05]** Danysh, A., and D. Tan, "Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit,"
*IEEE Trans. Computers*, Vol. 54, No. 3, pp. 284-293, March 2005.

Cites the computer arithmetic book [179].

**[Davi84]** Davis, W. A. and D.-L. Lee, "An Associative Memory Scheme,"
*Proc. Int'l Conf. Computers and Applications*, Beijing, June 1984, pp. 17-23.

Cites the *Proc. IEEE* 1973 survey [4].

**[Davi86]** Davis, W. A. and D.-L. Lee, "Fast Search Algorithms for Associative Memories,"
*IEEE Trans. Computers*, Vol. 35, No. 5, pp. 456-461, May 1986.

Cites the *Proc. IEEE* 1973 survey [4].

**[Dawi96]** Dawid, H. and H. Meyr, "The Differential CORDIC Algorithm: Constant Scale Factor Redundant Implementation Without Correcting Iterations,"
*IEEE Trans. Computers*, Vol. 45, No. 3, pp. 307-318, March 1996.

Cites the 1988, 1990, and 1993 papers on GSD arithmetic [56], [66], [86].

**[Dawi99]** Dawid, H. and H. Meyr, "CORDIC Algorithms and Architectures,"

in *Digital Signal Processing for Multimedia Systems*, ed. by K.K. Parhi and T. Nishitani, Marcel Dekker, 1999, pp. 623-655.

Cites the 1990 *IEEE TC* GSD paper [66].

**[DeCa04]** De Caro, D., E. Napoli, and A.G.M. Strollo, "Direct Digital Frequency Synthesizers with Polynomial Hyperfolding Technique,"
*IEEE Trans. Circuits and Systems II*, Vol. 51, No. 7, pp. 337-344, July 2004.

Cites the computer arithmetic book [179] as its reference [34].

**[Deca05]** Decayeux, C. and D. Seme, "3D Hexagonal Network: Modeling, Topological Properties, Addressing Scheme, and Optimal Routing Algorithm,"
*IEEE Trans. Parallel and Distributed Systems*, Vol. 16, No. 9, pp. 875-884, September 2005.

Cites the parallel processing book [162].

**[DeCa09]** De Caro, D., N. Petra, and A. G. M. Strollo, "High-Performance Special Function Unit for Programmable 3-D Graphics Processors,"
*IEEE Trans. Circuits and Systems I*, Vol. 56, No. 9, pp. 1968-1978, September 2009.

Cites the computer arithmetic book [179] as its reference [15].

**[Deig81]** Deighton, S. (Ed.), *Computers in Developing Countries—A Bibliography*,

IEE, London, 1981, Section 2.7.4.

Cites the 1977 informatics in Iran paper [24].

**[Desc06]** Deschamps, J.-P., G. J. A. Bioul, and G. D. Sutter, *Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems*,

Wiley-Interscience, 2006.

Cites the computer arithmetic book [179] in Chapters 3, 5, 6, and 16.

**[DeWi78]** DeWitt, D. J., "DIRECT — A Multiprocessor Organization for Supporting Relational Data Base Management Systems,"
*Proc. 5th Symp. Computer Architecture*, pp. 182-189, April 1978.

Cites the 1972 RAPID paper [2].

**[Dhil87]** Dhillon, B. S., *Reliability in Computer System Design*,

Ablex, 1987.

Cites the 1974 AFIPS Conf. paper on fault-tolerant parallel DSP [8].

**[Di03]** Di, J., and J. S. Yuan, "Power-Aware Pipelined Multiplier Design Based on 2-Dimensional Pipeline Gating,"
*Proc. 13th ACM Great Lakes Symp. VLSI*, April 2003, pp. 64-67.

Cites the computer arithmetic book [179].

**[Di06]** Di, J., J. S. Yuan, and R. Demara, "Improving Power-Awareness of Pipelined Array Multipliers Using Two-Dimensional Pipeline Gating and Its Application on FIR Design,"
*Integration, the VLSI Journal*, Vol. 39, No. 2, pp. 90-112, March 2006.

Cites the computer arithmetic book [179].

**[Dick08]** Dick, C., "CORDIC Architectures for FPGA Computing,"

Ch. 25 in *Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation*, ed. by S. Hauck and A. DeHon, Morgan Kaufmann, 2008, pp. 513-537.

Cites the computer arithmetic book [179].

**[Dimi05]** Dimitrakopoulos, G., and D. Nikolos, "High-Speed Parallel-Prefix VLSI Ling Adders,"
*IEEE Trans. Computers*, Vol. 54, No. 2, pp. 225-231, February 2005.

Cites the computer arithmetic book [179].

**[Dimi07]** Dimitroulakos, G., M. D. Galanis, N. Kostaras, and C. E. Goutis, "A Unified Evaluation Framework for Coarse Grained Reconfigurable Array Architectures,"
*Proc. 4th Int'l Conf. Computing Frontiers*, Ischia, Italy, May 7-9, 2007, pp. 161-171.

Cites the computer arithmetic book [179].

**[Dini99]** Dinitz, Y., S. Even, R. Kupershtok, and M. Zapolotsky, "Some Compact Layouts of the Butterfly,"
*Proc. 11th ACM Symp. on Parallel Algorithms and Architectures*, pp. 54-63, June 1999.

Cites a tech. report on layout and packaging of butterfly nets that led to the SPAA 2000 paper [185].

**[Dong09]** Dong, Q., X. Yang, and J. Zhao, "Fault Hamiltonicity and Fault Hamiltonian-Connectivity of Generalised Matching Networks,"
*Int'l J. Parallel, Emergent and Distributed Systems*, Vol. 24, No. 5, pp. 455-461, October 2009.

Cites the book on parallel processing [162].

**[Drap01]** Draper, B. A., A. P. W. Bohm, J. Hammes, W. Najjar, J. R. Beveridge, C. Ross, M. Chawathe, M. Desai, and J. Bins, "Compiling SA-C Programs to FPGAs: Performance Results,"
*Proc. 2nd Int'l Workshop Computer Vision Systems* (Lecture Notes in Computer Science, Vol. 2095), 2001, pp. 220-235.

Cites the computer arithmetic book [179].

**[Eber15]** Ebergen, J. and N. Jamadagni, "Radix-2 Division Algorithms with an Over-Redundant Digit Set,"
*IEEE Trans. Computers*, Vol. 64, No. 9, pp. 2652-2663, September 2015.

Cites the 2000 book on computer arithmetic [167].

**[Erce94]** Ercegovac, M. D. and T. Lang, *Division and Square Root: Digit-Recurrence Algorithms and Implementations*,

Kluwer, 1994.

Cites the 1990 *IEEE TC* GSD paper [66].

**[Erce98]** Ercegovac, M. D. and T. Lang, "Effective Coding for Fast Redundant Adders Using the Radix-2 Digit Set {0, 1, 2, 3},"
*Proc. Asilomar Conf. Signals, Systems, and Computers*, 1998, pp. 1163-1167.

Cites the 1989 IPPS parallel multiplier paper [58].

**[Erce04]** Ercegovac, M. D. and T. Lang, *Digital Arithmetic*,

Morgan Kaufmann, 2004.

Cites five papers on table look-up for convergence division [50], addition of recoded BSD numbers [56], GSD support functions [86], pipelined multioperand addition [135], and fast tree multipliers [136], plus the computer arithmetic book [179].

**[Even02]** Even, S. and R. Kupershtok, "Layout Area of the Hypercube,"
*Proc. 13th ACM-SIAM Symp. Discrete Algorithms*, January 2002, pp. 366-371.

Cites the 1999 paper on VLSI layout of hypercubic networks [164].

**[Fahm01]** Fahmy, H. A. H., A. A. Liddicoat, and M. J. Flynn, "Improving the Effectiveness of Floating-Point Arithmetic,"
*Proc. 35th Asilomar Conf. Signals, Systems, and Computers*, November 2001.

Cites the 1993 *IEEE TC* paper on arithmetic support functions for GSD [86].

**[Fahm02]** Fahmy, H. A. H., A. A. Liddicoat, and M. J. Flynn, "Parametric Time Delay Modeling for Floating Point Units,"
*Advanced Signal Processing Algorithms, Architectures, and Implementations XII* (Proc. SPIE Int'l Symp.), July 2002.

Cites the 1990 *IEEE TC* GSD paper [66].

**[Fahm03]** Fahmi, H. A. H. and M. J. Flynn, "The Case for a Redundant Format in Floating-Point Arithmetic,"
*Proc. 16th IEEE Symp. Computer Arithmetic*, June 2003, pp. 95-102.

Cites *IEEE TC* 1990 paper on GSD [66] and 1993 paper on arithmetic support functions [86].

**[Falk10]** Falkner, N., R. Sooriamurthi, and Z. Michalewicz, "Puzzle-Based Learning for Engineering and Computer Science,"
*IEEE Computer*, Vol. 43, No. 4, pp. 20-28, April 2010.

Cites the 2009 *IEEE Computer* paper on puzzling problems [252].

**[Fan05]** Fan, L.-J., C.-B. Yang, and S.-H. Shiau, "Routing Algorithms on the Bus-Based Hypercube Network,"
*IEEE Trans. Parallel and Distributed Systems*, Vol. 16, No. 4, pp. 335-348, April 2005.

Cites the 1993 *IEEE TPDS* paper on mesh with separable buses [90].

**[Fan07]** Fan, J., X. Jia, and X. Lin, "Optimal Embeddings of Paths with Various Lengths in Twisted Cubes,"
*IEEE Trans. Parallel and Distributed Systems*, Vol. 18, No. 4, pp. 511-522, April 2007.

Cites the 1999 *IEEE TPDS* paper on stable insertion sorter [163].

**[Farm13]** Farmahini-Farahani, A., H. J. Duwe III, M. J. Schulte, and K. Compton, "Modular Design of High-Throughput, Low-Latency Sorting Units,"
*IEEE Trans. Computers*, Vol. 62, No. 7, pp. 1389-1402, July 2013.

Cites the 1999 *IEEE TPDS* paper on stable insertion sorter [163].

**[Fars83]** Farsi, H. and J. Tartar, "A Relational Data Base Machine Employing Associative Memories and Transposed Files,"
*Proc. ACM Annual Conference Computers: Extending the Human Resource*, pp. 193-199, January 1983.

Cites the *Proc. IEEE* 1973 survey paper [4].

**[Faym99]** Fayman, J. A., P. Pirjanian, H. I. Christensen, and E. Rivlin, "Exploiting Process Integration and Composition in the Context of Active Vision,"
*IEEE Trans. Systems, Man and Cybernetics, Part C*, Vol. 29, No. 1, pp. 73-86, February 1999.

Cites the 1994 *IEEE TR* paper on voting algorithms [101].

**[Feng77]** Feng, T.-Y., "Guest Editorial: An Overview of Parallel Processors and Processing,"
*ACM Computing Surveys*, Vol. 9, No. 1, pp. 1-2, January 1977.

Cites the *Proc. IEEE* 1973 survey paper [4].

**[Fitf09]** Fit-Florea, A., L. Li, M. A. Thornton, and D. W. Matula, "A Discrete Logarithm Number System for Integer Arithmetic Modulo 2^{k}: Algorithms and Lookup Structures,"
*IEEE Trans. Computers*, Vol. 58, No. 2, February 2009, pp. 163-174.

Cites the book on computer arithmetic [179].

**[Fran08]** Francq, J., J.-B. Rigaud, P. Manet, A. Tria, and A. Tisserand, "Error Detection for Borrow-Save Adders Dedicated to ECC Unit,"
*Proc. 5th Int'l Workshop Fault Diagnosis and Tolerance in Cryptography*, 2008, pp. 77-86.

Cites the 2006 Asilomar Conf. paper on fault-tolerant reversible circuits [228].

**[Frek97]** Freking, W. L. and K. K. Parhi, "Low-Power FIR Digital Filters Using Residue Arithmetic,"
*Proc. 31st Asilomar Conf. Signals Systems and Computers*, November 1997, pp. 739-743.

Cites the 1996 Signal Processing paper on hybrid RNS-binary arithmetic [129].

**[Frek99]** Freking, W. L. and K. K. Parhi, "Montgomery Modular Multiplication and Exponentiation in the Residue Number System,"
*Proc. 33rd Asilomar Conf. Signals Systems and Computers*, October 1999, pp. 1312-1316.

Cites the 1994 *IPL* paper on RNS division [97] as a seminal work.

**[Frek00]** Freking, W. L. and K. K. Parhi, "Modular Multiplication in the Residue Number System with Application to Massively-Parallel Public-Key Cryptography Systems,"
*Proc. 34th Asilomar Conf. Signals Systems and Computers*, October 2000, pp. 1339-1343.

Cites the 1994i>IPLpaper on RNS division [97].

**[Gait84]** Gaitanis, N., "Totally Self Checking Checkers for Low Cost Arithmetic Codes,"
*Proc. Fault-Tolerant Computing Symp.*, pp. 260-264, 1984.

Cites the *IEEE TC* 1978 arithmetic error code paper [28].

**[Gao11]** Gao, X., Y. Luo, and W. Liu, "Resistance Distances and the Kirchhoff Index in Cayley Graphs,"
*Discrete Applied Mathematics*, Vol. 159, No. 17, pp. 2050-2057, October 2011.

Cites the 2007 *DAM* paper on hex and honeycomb meshes as Cayley graphs [236].

**[Garc03]** Garcia, F., J. Solano, I. Stojmenovic, and M. Stojmenovic, "Higher Dimensional Hexagonal Networks,"
*J. Parallel and Distributed Computing*, Vol. 63, pp. 1164-1172, 2003.

Cites the 2001 *IEEE TPDS* paper on unified formulation of honeycomb and diamond networks [191].

**[Garo11]** Garofalo, V., N. Petra, and E. Napoli, "Analytical Calculation of the Maximum Error for a Family of Truncated Multipliers Providing Minimum Mean Square Error,"
*IEEE Trans. Computers*, Vol. 60, No. 9, pp. 1354-1365, September 2011.

Cites the book on computer arithmetic [179].

**[Gash07]** Gashi, I., P. Popov, and L. Strigini, "Fault Tolerance via Diversity for Off-the-Shelf Products: A Study with SQL Database Servers,"
*IEEE Trans. Dependable and Secure Computing*, Vol. 4, No. 4, pp. 280-294, October-December 2007.

Cites the book chapter on voting [223].

**[Gonz00]** Gonzalez, A. F. and P. Mazumdar, "Redundant Arithmetic, Algorithms and Implementations,"
*Integration, the VLSI Journal*, Vol. 30, No. 1, pp. 13-53, November 2000.

Cites the 1990 *IEEE TC* GSD paper [66] and uses it extensively for notation and examples.

**[Gorg09]** Gorgin, S. and G. Jaberipur, "Fully Redundant Decimal Arithmetic,"
*Proc. 19th IEEE Symp. Computer Arithmetic*, June 2009, pp. 145-152.

Cites the 1990 *IEEE TC* paper on GSD representation [66].

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Describes RAPID [2] in some detail.

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Cites the 1990 *IEEE TC* paper on GSD representations [66].

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