Hybrid Silicon Process Overview

Summary

The hybrid silicon process can be summarized as follows:
(1) Silicon-layer processing
Starting with an SOI (Silicon on Insulator) wafer, rib waveguides are patterned in the top silicon and vertical channels are etched to the buried oxide (the purpose of these vertical channels is to allow outgasing during bonding steps later in the process). Additional steps to introduce diodes into the silicon through doping are also possible, as are additional etch steps for gratings.
(2) III-V bonding and processing
III-V epi material is then die-bonded to the silicon and back-polished until a thin stack of III-V remains, after which wet etching removes the remainder of excess Indium Phosphide (there is typically a p-contact layer of InGaAs beneath this which acts as an etch stop). Gain elements are then patterned in the III-V by etching down through the epi stack roughly to the quantum wells (this patterned stack is then referred to as the "mesa"), a second etch step goes through the quantum wells to the n-InP, and finally the n-InP can be etched until the underlying silicon is exposed.
(3) Metallization
Thick p-contact metal is deposited on top of the mesa (although thin metal may already have been deposited for this purpose during the mesa definition). The mesa is then typically either subjected to a proton implantation step or an etch step to confine current to a narrow path directly beneath the p-contact. Metal for n-contacts is deposited, and a "buffer" layer (SU8, BCB, oxide, or some other dielectric) is added to allow metal traces to be overlaid on top of the waveguides without impacting the optical mode. Vias are etched through the buffer and "probe" metal (i.e. thick metal for probing and wirebonding) is deposited on top and patterned.

The actual process used to accomplish these steps is dependent on the project; in many of these steps there are a range of options available for processing. Below is a core process which should be considered the "template"; additional modules can be added to this as desired - these are provided below the core process along with a description of what they provide and their current status.

Core process

This is the core process which should be considered the "template"; additional modules can be added to this as desired.

Core Process Outline

Core process steps

Process ID	Index	Process follower	Description	Test Structures	Expert
Chip and Wafer Sizing	0	Sizing Notes	Size and shape rationale and requirements.		Mike D
WG etch	1	Si WG etch‎ Caution out of date	Rib waveguide formation, Alignment marks.		Mike D
VC etch	2	Si VC etch	Vertical channel etch		Sudha S
Bonding	3	Short guide	Plasma assisted wafer bonding full guide - Author:Michael D		Mike D
InP-mesa etch	4	P-mesa etch	Mesa etch to top SCH layer		Mike D
QW wet etch	5	QW etch	Active layer wet etch		Mike D
N-metal deposition	6	N-metal deposition Caution out of date	N-metal (Ni/Ge/Au/Ni/Au)		Mike D
Buffer & Via formation	7	Planarization & Via etch	1um oxide deposition & via etch		Mike D
P-/Probepad metal deposition	8	Probepad metallization	P-/probepad metal stack (Pd/Ti/Pd/Au)		Mike D

Optional process modules

These are process "modules" which can be selected as needed and added to the Core process (in some cases as alternatives to core process steps).
The established maturity (and therefore yield) of each module varies; add modules to suit individual applications, but be aware that each deviation from the core process introduces additional risk. These modules should be added in the order shown in the Index if possible (e.g. Index 1.5 indicates that the process goes between process 1 and 2, etc.), and absolutely must be added according to the Process Placement Rules.

Status codes (Risk):
1 = established (can be dropped into the process with little first-order risk - this does not rule out risk from incompatibility with other modules)
2 = used frequently, but still subject to significant risks
3 = tested successfully at least once, but high risk
4 = not yet demonstrated at UCSB, expect considerable process development

Optional process modules

Process ID	Index	Process follower	Description	Process Placement Rules	Test Structures	Expert	Status
Shallow gratings	2.2	Grating process	Shallow (<200nm) surface gratings in top Si	Add-on after VC step (can be combined with Deep gratings for double-depth features)		Jock	1
Deep gratings	2.3	Grating process	Deep (>200nm) surface gratings in top Si	Add-on after VC step (can be combined with Shallow gratings for double-depth features)		Jock	3
SOI Actives	2.4	Si actives‎	Introduces diodes into the silicon layer	Must precede III-V bonding	mask file measurement guide	JKD	3
SOI PDs	2.5	Si PDs‎	Renders diodes in the silicon layer into photodiodes	Back-end step (can be after probe metal); must be preceded by SOI Actives		JKD	4
Protection layer	2.6	protection layer	Protects exposed Si for selective die-bonding	immediately prior to III-V bonding (co-requires Gapfill/GFR modules)		JKD	3
Gapfill	3.5	Gapfill	adds protection in the "gap" between III-V die and protected Si	immediately post III-V bonding (co-requires Protection/GFR modules)		JKD	3
Quantum Well Intermixing	3.7	QWI	Allows III-V bandgap adjustment in selected regions	add-on post-bond		Sid	3
GF Removal (GFR)	5.5	GFR	removes protection layers and III-V in the "gap"	back-end step		JKD	3
N-InP definition	6.5	N-InP etch	Removes excess n-InP (may reduce loss)	Add-on after n-metal deposition		Mike D	2
Polymer Buffer	7	?	SU8 or BCB polymer buffer (useful for high-speed rf) and vias	Replaces Core Buffer/Via step		?	4
Proton implantation	8.5	proton implantation	Defines current channel in the mesa by proton implantation. Implant recipes‎	add after first thick metal dep (use thick metal as the channel mask)		JKD	1

Appendix

Please contact JKD before making changes to this page.

The old hybrid silicon page can be found here.
The slides from the HSP meeting can be found here

Additional information:
- Spreadsheet showing the modules used in various recent fabrication runs: HSP v 1.0.0