Jun 2 (Thu) @ 4:00pm: "Hardware Modeling and Efficient Architectural Exploration for Machine Learning Accelerators,” Tianqi Tang, ECE PhD Defense

Abstract

The innovation in computer architecture and the development of simulation tools are influencing each other mutually. The booming of machine learning drives the need for new modeling tools for new architectures and applications. Meanwhile, the continuous evolution of ML models drives the need to know how well the domain-specific accelerators can be adaptive to a broad spectrum of ML workloads with satisfying performance and high utilization at the early design stage.

To address those challenges, this talk focuses on the hardware modeling and efficient architectural exploration of the machine learning accelerators. The hardware modeling is conducted from two perspectives. First, we will introduce NeuroMeter, an integrated power, area, and timing modeling framework for ML accelerators. It enables the runtime analysis of system-level performance and efficiency at the pre-RTL design stage. We then develop the cost model with the emphasis on the 2.5D integration and chiplet system. Leveraging the proposed hardware modeling, we further discuss the efficient architectural design for deep learning workloads under different scenarios. Two board classes of architectures are explored, i.e. the brawny design, which adopts small numbers of large cores; and the wimpy design, which adopts large numbers of small cores. This talk explores the pros and cons of these two classes of architectures; and further proposes a reconfigurable systolic array based architecture which has the advantages of both these two architectures with negligible overheads.

Bio

Tianqi Tang received her B.S. degree in 2014 and her M.S. degree in 2017 from the Department of Electronic Engineering, Tsinghua University, Beijing, China. She is currently pursuing the Ph.D. degree at the Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA, USA. Her research interests include hardware modeling, domain specific accelerator, and algorithm/hardware co-design.

Hosted by: Yuan Xie

Submitted by: Tianqi Tang <tianqi_tang@ucsb.edu>